As state-of-the-art computer systems and circuits evolve, there is a continuing need for higher performance bipolar junction transistors capable of operating at higher switching speeds, with increasing degrees of device integration, and with low rate of failure. There is also a continuing need to shrink or scale down device size to obtain improved device performance. In order to obtain further advances in device scaling, improved lithographic techniques and equipment must be developed. Unfortunately, the lithographic patterning tolerances of state-of-the-art equipment is rapidly reaching its limits. The range of future device geometries and contact line widths require extremely small dimensions. Thus, lithographic errors within the normal tolerance range can impede efforts to further shrink device size. Accordingly, it would be advantageous to develop processes and device geometries less dependent on photolithographic accuracy.
Attempts to reduce dependency on photolithographic accuracy typically include the steps of self-aligning various active regions of the bipolar junction transistor to each other. In a "self-aligned" process, at least one device region is used as an alignment guide for forming a subsequent region(s). Accordingly, self-aligned fabrication processes are less dependent upon precise photolithographic alignment than similarly directed non self-aligned processes. Faster switching speeds can also be obtained, in part, by reducing the lateral and vertical size and parasitic components of individual transistors and increasing the degree of integration. Typical parasitics include base resistance, r.sub.b, base-collector capacitance, C.sub.bc, collector resistance, r.sub.c, and collector-substrate capacitance, C.sub.cs. As these parasitic components are reduced, device performance improves because faster device operation and lower power consumption is possible.
As will be understood by those skilled in the art, attempts to reduce power consumption in bipolar junction transistors have included the use of double-poly structures. But, double-poly structures have suffered from a partial dopant depletion phenomenon associated with the emitter region. An attempt to form improved bipolar junction transistors has also been disclosed in an article by Wim Van der Wel et al., entitled "Poly-Ridge Emifter Transistor (PRET): Simple Low-Power Option to a Bipolar Process", Proceedings IEDM, pp. 453-456 (1993). According to the structure of the disclosed bipolar transistor, an emitter having a width of less than 0.1 .mu.m may be formed by employing general processing steps instead of more improved lithographic technology. Thus, a bipolar transistor having high performance and low-power consumption can be formed. Unfortunately, the PRET device may suffer from increased parasitic junction capacitance between the base-collector junction.
Thus, notwithstanding the above attempts to form high performance bipolar junction transistors, there continues to be a need for improved methods of forming bipolar junction transistors having reduced dimensions and reduced parasitic junction capacitances.